1. Field of the Invention
This invention relates to a drive circuit for a liquid crystal display device (generally abbreviated to "LCD") for supplying analog driving voltages for displaying desired image data to selected pixels among a plurality of pixels that constitute a liquid crystal display panel of the liquid crystal display device, a liquid crystal display device equipped with this kind of drive circuit, and a method for driving the liquid crystal display device.
More particularly, the present invention is directed to an active-matrix type liquid crystal display device for executing gradation display by writing image data to pixels to be selected, by utilizing ON/OFF operations of TFTs (Thin Film Transistors), etc., connected to the pixels of the liquid crystal cells disposed at the points of intersection between a plurality of parallel, first bus lines for serially scanning the pixels (first bus lines are generally referred to as "scan bus lines") and second bus lines crossing orthogonally these first bus lines and supplying a write voltage (driving voltage) in accordance with the gradation to be displayed (second bus lines are generally referred to as "data lines").
Thin and light-weight display devices, such as liquid crystal display devices, are generally used for portable personal computers. These kinds of liquid crystal display devices are expected to be used as the display devices which will replace CRTs (Cathode-Ray Tubes), and a technical development has been vigorously done. Among these liquid crystal display devices, an active-matrix type liquid crystal display device employing the driving system by the TFTs described above is very promising because its display speed is high and its display quality is excellent.
In the latest application software, a multiple-color display system for displaying a variety of colors by various combinations of variable densities (gradations) of three primary colors, that is, red, blue and green, has become general. Therefore, the performance of such application software cannot be fully exploited when the number of gradations capable of displaying each primary color is small. For this reason, the liquid crystal display device described above needs a drive circuit suitable for multiple-stage gradations capable of generating write voltages of various magnitudes in accordance with the gradation data to be displayed.
2. Description of the Related Art
The construction of a drive circuit for a liquid crystal display device according to the prior art will be hereby explained with reference to the accompanying drawings (FIGS. 1 to 12) in order to have the problem in the conventional drive system in the active-matrix type liquid crystal display device more easily understood.
To begin with, the conventional structural example of the active-matrix type liquid crystal display device using the TFTs described above, and a drive circuit for driving such a liquid crystal display device, will be explained with reference to FIGS. 1 to 5.
FIGS. 1 and 2 are circuit block diagrams showing the constructions of the first and second portions of a conventional liquid crystal display device, respectively; FIGS. 3 and 4 are circuit block diagrams showing the first and second portions of the principal part of the conventional liquid crystal display device shown in FIGS. 1 and 2, respectively; and FIG. 5 is a circuit diagram showing a detailed example of a liquid crystal display panel shown in FIG. 2.
In order to simplify the explanation of the liquid crystal display device, however, it will be hereby assumed that a liquid crystal display panel 10 has a pixel number comprising a 4.times.4 matrix, and a system for controlling the display of image data is a so-called "digital driver system".
Symbols P11 to P44 that constitute the liquid crystal display panel 10 (FIG. 2) in the liquid crystal display device shown in FIGS. 1 and 2 represent a plurality of pixels each defined as the smallest unit for displaying image data. Further, transistor switch devices Q11 to Q44, each comprising a TFT, are connected to these pixels P11 to P44 as shown in FIG. 5. Each of these transistor switch devices Q11 to Q44 play a role of a switch when a signal voltage for displaying the gradation of the image data to liquid crystal capacities Cmn [where m and n represent the number of data lines (number of column electrodes) and the number of scan bus lines (number of row electrodes), respectively; m and n=1 to 4, respectively; and Cmn=C11 to C44 in this explanation]. In FIG. 5, a line of pixels in the transverse direction, that is, a line of pixels in the direction extending along each of the scan bus lines Y1 to Y4, is called "one line". Data for displaying image data to the liquid crystal display device is written to each line of the scan bus lines, and such operations are repeated 60 times per second so as to provide images devoid of flickers when a person watches the images with his own eyes.
Further, as shown in FIG. 5, the data lines X1 to X4 comprise a kind of a distributed constant circuit which in turn includes distributed resistors r11 to r44 and distributed capacities c11 to c44. Each of the distributed resistors r11 to r44 is made of a material forming the data line, and each of the distributed capacities c11 to c44 has a synthesized value which is obtained by synthesizing a capacitance brought about by defining a liquid crystal interposed between the data line and the opposed electrode as a dielectric and a capacitance brought about by defining an insulator at the point of intersection between the data line and the scan bus line as a dielectric, as the main capacitive components.
The number of pixels inside the liquid crystal display panel 10 in the practical liquid crystal display device is generally much larger than the number of pixels of the conventional liquid crystal display device shown in the explanatory view of FIGS. 1 to 5. Typically, a liquid crystal display device having about 640 pixels in the transverse direction of the liquid crystal display panel 10 (in the direction along the scan bus lines) and about 480 pixels in the longitudinal direction (in the direction along the data lines) is ordinarily available. However, in this case, the liquid crystal display device comprising a 4.times.4 matrix is hereby illustrated for ease of explanation. Furthermore, in order to effect color display, pixels must be provided for each of R (Red), G (Green) and B (Blue).
Now, the explanation will be hereby given as to how the image data can be correctly written into each pixel with reference to FIGS. 1 and 2. In FIGS. 1 and 2, a control circuit portion 400 for controlling various operations of all the drive circuits inclusive of the below-mentioned data driver unit 200 and scan driver 30 is shown disposed.
A horizontal synchronous signal (generally abbreviated to "sync signal") HS representing the scanning cycle when displaying the image data (that is, the signal representing the cycle for each line), a vertical sync signal VS for inputting the image data per frame from the upper end of the display surface (that is, the signal representing the cycle per frame), and other control signals are inputted to this control circuit portion 400. Symbols D1 to DN inputted to the control circuit portion 400 represents binary image data, and symbol N represents the bit number for effecting gradation display. Symbols CLK inputted to the control circuit portion 400 represents the timing signal (clock signal) applied in synchronism with the image data. This clock signal sets the timing for writing the image data D1 to DN. However, because the clock signal CLK can be generated inside the drive circuit by measuring the cycle of the horizontal sync signal HS, it is not essentially necessary as one of the interfaces.
In FIG. 1, further, reference numeral 210 denotes a shift register. This shift register 210 generates timing signals TS1 to TS4 for serially writing display data to the first memories 610 to 640, when the start signal T1 representing the start of the display of the image data for each line and the clock CK1 for advancing the register are delivered for every line from the control circuit 400. Each of these first memories 610 to 640 comprises a memory having an N-bit memory capacity, and image data DT1 to DTN having an N-bit parallel system are stored in these first memories 610 to 640, respectively. Second memories 710 to 740, too, comprise a memory having an N-bit memory capacity. In this construction, soon after the image data are written into the first memories 610 to 640, the image data stored in the first memories 610 to 640 for one line (scan bus line) are simultaneously written into the second memories 710 to 740 by the write control signal T2 before the data of the next line (scan bus line) arrive.
In FIG. 1, further, selectors 910 to 940 are disposed on the output side of the second memories 710 to 740. These selectors 910 to 940 are deemed to be a kind of digital-to-analog conversion circuit for generating analog signals corresponding to the digital data stored in the second memories 710 to 740. Decoders 810 to 840 interposed between the selectors 910 to 940 and the second memories 710 to 740 decode the image data represented by the binary number and generate a signal for turning ON only one analog switch inside each of the selectors 910 to 940. In this way, each of the selectors 910 to 940 selects any one of M kinds (V1 to VM) of voltages and output the thus selected voltage to the data lines X1 to X4. The M kinds of voltages V1 to VM and the N-bit data stored in the second memories 710 to 740 have the relation M=2.sup.N when the data are represented by the binary number. When it is assumed that N=3, for example, it is derived that M=8, and when it is assumed that N=4, it is derived that M=16.
The whole circuit gathering the shift register 210, the first memories 610 to 640, the second memories 710 to 740, the decoders 810 to 840, and the selectors 910 to 940 is generally integrated (into an IC circuit) as a data driver (generally abbreviated to "DD") unit, and it is represented by reference numeral 200 in FIG. 1. In FIG. 1, further, a reference power source unit 500 for generating a plurality of kinds of reference voltages VA to VX is not generally included in the integrated circuit. As for this reason, it can be mentioned that the data driver necessary for constituting a drive circuit of a display device generally comprises a plurality of ICs, whereas the reference power source unit 500 may be only one common power source and it is not advantageous to constitute a power source capable of supplying a large current inside an integrated circuit.
Further, the portion represented by reference numeral 510 inside the data driver unit 200 shown in FIG. 1 is a circuit which generates M kinds, that is, V1 to VM, of second reference voltages by dividing the first reference voltages VA to VX outputted from the reference power source unit 500 by a plurality of divided type resistors (i.e., voltage dividing resistors), that is, a resistor dividing circuit portion. In the construction of the main part of the liquid crystal display device (inclusive of the drive circuit) shown in FIGS. 3 and 4, an example is illustrated in which eight kinds of second reference voltages V1 to V8 (i.e., a plurality of kinds of the second reference voltages about twice as many as kinds of the first reference voltages) are finally generated from five kinds of the first reference voltages VA to VE. In this case, a larger number of kinds of reference voltages can be generated by increasing the number of division of a plurality of voltage dividing resistors.
In order to write the data voltages outputted from the data driver unit 200 and sent to the data lines X1 to X4, into the liquid crystal capacities through the TFTs, each of these TFTs functioning as an analog switch must be turned ON and OFF by controlling the gate voltage of each TFT. It is the scan driver (generally abbreviated to "SD") unit 30 that plays such a function as an analog switch. The scan driver unit 30 comprises a shift register 31 and driver units DV1 to DV4. The shift register 31 is a register which starts its operation by the start signal T3 and advances in accordance with the clock CK2. The start signal T3 has the same cycle as the vertical sync signal, and the clock CK2 has the same cycle as the horizontal sync signal. The shift registers 31 serially generates signals for turning ON the TFTs for every line of the liquid crystal display panel 10 (these signals are called the "scan signals").
Further, each of the driver units DV1 to DV4 shown in FIG. 2 has a function of a conversion circuit for effecting level conversion from the output of the shift register 31 to a voltage capable of controlling the ON/OFF operations of the TFTs, and it can be regarded as a binary output circuit which generates either a voltage capable of turning OFF the TFTs or a voltage capable of turning them ON.
FIGS. 3 and 4 are views showing in detail the selector 910 including a plurality of analog switches (eight switches, in FIG. 3), the decoder 810, the resistor dividing circuit portion 510, and the reference power source unit 500 shown in FIG. 1 and 2. The drawings illustrate the example in which one voltage is selected from among V1 to V8 by turning ON only one analog switch inside the selector 910. In other words, the example shows the case in which N described above is 3.
The explanation will be given in further detail. The decoder 810 (FIG. 3) includes three NOT devices 850-1 to 850-3 to which the binary image data D1 to D3 are inputted; four AND devices 860-1 to 860-4 which decode the image data outputted from these NOT devices 850-1 to 850-3; and NOR devices 870-1 to 870-8 which are connected to the output side of these AND devices 860-1 to 860-4, and which generate a control signal for turning ON one of the eight analog switches inside the selectors 910 to 940.
Further, the reference power source unit 500 includes one power source VR, five voltage dividing resistors RA to RE for dividing this power source VR and generating five kinds of the first reference voltages VA to VE, and buffer amplifiers A1 to A5 for sending the reference voltages from these voltage dividing resistors RA to RE to the resistor dividing circuit portion 510.
The resistor dividing circuit portion 510 includes eight voltage dividing resistors R1 to R8 in order to generate eight kinds of the second reference voltages V1 to V8 by further dividing the five kinds of the first reference voltages VA to VE from the buffer amplifiers A1 to A5.
The example shown in FIGS. 1 and 2 deals with a simple image having a 4.times.4 matrix in order to explain the driving method according to the prior art. However, as described before, the practical liquid crystal display device generally drives 640 lines of pixels in the transverse direction and 480 lines of pixels in the vertical direction, or 640.times.480=307,200 pixels in total. Therefore, the size of the data driver unit for this purpose becomes relatively large in scale. Moreover, in order to effect color display, separate pixels are necessary for each of R, G and B. Therefore, the total value of the number of pixels becomes three times as large as the value given above (307,200 pixels). Further, to accomplish gradation display so as to make the color display more closely approach to a full color display, the number of bits of the data driver unit, described with reference to FIGS. 1 and 2, must be increased.
FIGS. 3 and 4 illustrate an example equipped with a data driver unit having a 3-bit configuration or 8-value (2.sup.3 =8) configuration. The number of gradations required for each color to express 260,000 colors (called a "full color display") is sixty-four (64). In this case, 64 analog switches are necessary inside each selector, and 64 kinds of voltages are necessary from the resistor dividing circuit portion 510. The IC constituting the driver inclusive of the data driver unit 20 is generally formed on the basis of a fabrication technology of MOSs (Metal Oxide Semiconductors). With regard to the fabrication technology of the MOSs, it is extremely easy to produce a small-sized analog switch and there is no serious problem. However, to obtain finally 64 kinds of reference voltages, 64 terminals are necessary at the terminal portions of a plurality of integrated circuits (IC1 and IC2) 42 and 44 in the liquid crystal display device shown in FIG. 12, and this is one of the greatest problems for putting a multi-gradation driver into practical application.
When the number of necessary terminals increases as described above, a wiring region of this reference power source line Lr has a relatively large width. Therefore, a frame portion of the display screen of the liquid crystal display panel 10 cannot be reduced, so that the liquid crystal display device cannot be made compact. In other words, the display screen of a portable notebook type personal computer used as the useful application of the liquid crystal display device cannot be easily enlarged. To cope with this problem, an attempt has been made to decrease the number of signal lines extending from the resistor dividing circuit portion 510 through the integrated circuits 42 and 44, and to increase the number of reference voltages inside the integrated circuits.
However, even the drive system of the liquid crystal display device according to the prior art described above is not yet free from the following problem. The problem encountered when the liquid crystal display panel is driven by using the drive circuit of the liquid crystal display device according to the prior art is shown in FIGS. 6 to 11.
FIGS. 6 and 7 show the first portion and the second portion of the circuit diagram for explaining the problem of the drive circuit of the liquid crystal display device according to the prior art, respectively; FIG. 8 is a timing chart for explaining the problem of the drive circuit of the liquid crystal display device according to the prior art; FIGS. 9 and 10 show the first portion and the second portion of an equivalent circuit diagram for explaining in more detail the problem of the prior art system, respectively; and FIG. 11 is a timing chart for explaining in further detail the problem of the prior art system.
The particular problem in the drive circuit of the conventional liquid crystal display device is that excessive power consumption occurs due to the current flowing steadily through the resistor dividing circuit portion. More concretely, as shown in FIGS. 6 and 7, the current It flowing from the resistor dividing circuit portion into the liquid crystal display panel is a transient current which becomes zero when charging of the distributed capacities c11 to c41 of the data line (e.g. X1) is finished. In contrast, the current Is supplied from the reference power source unit to the resistor dividing circuit portion is a steady state current and remains constant. FIG. 8 shows the mode of the changes of these transient current It and steady current Is and the change of the voltage VX1 on the data line X1 (hereinafter merely called the voltage "VX") with respect to the horizontal sync signal HS, the scan signals supplied to the scan bus lines Y1 to Y4 and the write control signal T2. The current value of the steady state current Is can become small in inverse proportion to the dividing resistance value of the voltage dividing resistor by increasing this resistance value, but when the resistance value is increased, the time constant required for charging the data line up to the predetermined voltage level becomes larger as shown in FIG. 11, and therefore an accurate gradation voltage cannot be written into the liquid crystal capacities within the period in which a scan voltage (i.e., scan signal) is supplied to each of the scan bus lines Y1 to Y4.
Therefore, in order to have the problem resulting from the voltage dividing resistors more easily understood, an example of calculation of numerical values on the basis of the equivalent circuit diagrams of FIGS. 9 and 10 will be given. By the way, symbols R, RS, RD and C in FIGS. 9 and 10 represent the resistance value of the voltage dividing resistor, the resistance value of the equivalent resistor of the analog switch, the resistance value of the equivalent resistor of the data line and the capacitance value of the equivalent distributed capacity of the data line, respectively.
It will be hereby assumed that the resistance value R of one voltage dividing resistor is 1 k.OMEGA., the capacitance value C of the equivalent distributed capacity of the data line is 100 pF and the number of data lines is 240. Then, the resistance value of the equivalent output resistor of the resistor dividing circuit portion is, in the worst case (the case in which all the image data are the same), NR/2 (NR/2=240.times.1,000/2=120 k.OMEGA.) by simplifying the equivalent circuit for charging a portion (1) of FIG. 9 into the equivalent circuit such as a portion (2). Therefore, even when the resistance value RS of the equivalent resistor of the analog switch and the resistance value RD of the equivalent resistor of the data line are set to zero, the time constant for charging the data line is 120 k.OMEGA..times.100 pF=12 .mu.sec. In consequence, the charging of the data line can be carried out up to only 81% of the final value of the voltage VX within the period of 20 .mu.sec permitted as the charging time of the data line [20 .mu.sec is a typical value in an example of the number of pixels in a conventional VGA (Video Graphic Array)].
In contrast, when the resistance value R of the voltage dividing resistor is set to 250.OMEGA., the time constant for charging the data line is 3 .mu.sec, and the charging of the data line can be carried out up to 99.8% within the period of 20 .mu.sec. The resistance value RS and the resistance value RD are set to zero in this calculation, but the resistance value RS of several k.OMEGA. is likely to be practically brought about, and the resistance value RD is typically the value from 10 to 20 k.OMEGA.. Therefore, the resistance value of the voltage dividing resistor must be further decreased to a smaller value (the equivalent circuit of portions (3) and (4) in FIG. 10 is approximate to the equivalent circuit for actually charging the data line).
When the resistance value R of the voltage dividing resistor is 100.OMEGA., for example, the resistance value of the equivalent resistance for the worst case is 12 k.OMEGA.. When the resistance value of the data line is 20 k.OMEGA. and the ON resistance during ON state of the analog switch is 5 k.OMEGA., the time constant for charging the data line is (12+20+5) k.OMEGA..times.100 pF=3.7 .mu.sec, and according to the same calculation procedure as in an example mentioned above (i.e., the case in which the resistance value R is 250.OMEGA.), the charging of the data line can be carried out up to 99.5%.
As can be understood from the calculation results described above, the resistance value of each voltage dividing resistor must be about 100.OMEGA.. When the difference between a certain reference voltage V8 and another reference voltage V1 is 3V (a typical value necessary when driving a conventional liquid crystal display device), in this case, the steady state current Is is 3/800.OMEGA.=3.75 mA. Therefore, power consumption consumed by the portion having the voltage dividing resistors is 5V.times.3.75 mA.apprxeq.19 mW when the voltage value of the reference voltage V8 is 5V. This value is a calculation example in the case of the number of data lines of 240. Therefore, in the case of the number of data lines 640.times.3=1,920 for a color liquid crystal display device having the VGA pixels, power consumption is 19 mW.times.8=152 mW as large as eight times that consumed in the above calculation example.
As described above, the resistance value of the voltage dividing resistors must coincide with the characteristics of the liquid crystal display panel. However, when the resistance value is too small, power consumption increases, and when the resistance value is too large, a write voltage for the liquid crystal display panel becomes insufficient
It is difficult in the IC type data driver unit, on the other hand, to change the value of the voltage dividing resistors in accordance with the characteristics of the liquid crystal display panel, and therefore the voltage dividing resistors must be designed so as to have a margin to some degree for their driving capacity. Thus, the drawback are brought about that unnecessary power consumption occurs. Since notebook type personal computers having a built-in TFT type color liquid crystal display panel will become widespread rapidly in future, a drive circuit of a low power consumption type liquid crystal display panel becomes naturally necessary. Though the prior art drive system described above is an advantageous system in that the frame portion of the display screen of the liquid crystal display panel can become small, it is obvious that the problem occurs regarding the increase of power consumption due to the voltage dividing resistors inside the resistor dividing circuit portion in the prior art drive system.